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Instruction scheduling
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21	Eliminating Cache-Based Timing Attacks with Instruction-Based Scheduling Deian Stefan1 , Pablo Buiras2 , Edward Z. Yang1 , Amit Levy1 , David Terei1 , Alejandro Russo2 , and David Mazières1 1 Add to Reading List Source URL: www.scs.stanford.edu Language: English - Date: 2013-09-10 17:45:07 Computer architecture CPU cache Cache Scheduling Thread System Idle Process Cray MTA Computing Central processing unit Computer memory
22	ECE 554: Computer Architecture IN OUT Concepts: Add to Reading List Source URL: www.engr.colostate.edu Language: English - Date: 2009-01-05 17:37:43 Parallel computing Microprocessors Compiler optimizations Classes of computers Microarchitecture Instruction-level parallelism Central processing unit Multi-core processor Instruction scheduling Computing Computer architecture Concurrent computing
23	Resource-Constrained Software Pipelining Alexandru Nicolau Department of Information and Computer Science University of California, Irvine Irvine, CA 92717 Add to Reading List Source URL: theory.stanford.edu Language: English - Date: 2014-08-19 20:12:12 Compiler optimizations Computer architecture Software pipelining Operations research Scheduling Futures and promises Algorithm Pipeline Very long instruction word Concurrent computing Computing Parallel computing
24	Formal Verification of Translation Validators A Case Study on Instruction Scheduling Optimizations Jean-Baptiste Tristan Xavier Leroy Add to Reading List Source URL: pauillac.inria.fr Language: English - Date: 2007-11-09 01:03:49 Computing Programming language theory Compiler construction Models of computation Instruction scheduling Denotational semantics Trace scheduling Abstract interpretation Assembly language Compiler optimizations Programming language implementation Software engineering
25	INTERPROCESSOR COMMUNICATION SEEN AS LOAD-STORE INSTRUCTION GENERALIZATION Manolis G.H. Katevenis† Institute of Computer Science, Foundation for Research and Technology - Hellas (FORTH-ICS), Vassilika Vouton, Heraklion Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2013-12-23 07:16:59 Computer architecture CPU cache Scratchpad memory Direct memory access Multi-core processor Cell Remote direct memory access Cache Scheduling Computer hardware Computing Computer memory
26	Formal Verification of Translation Validators A Case Study on Instruction Scheduling Optimizations Jean-Baptiste Tristan Xavier Leroy Add to Reading List Source URL: gallium.inria.fr Language: English - Date: 2007-11-09 01:03:49 Computing Programming language theory Compiler construction Models of computation Instruction scheduling Denotational semantics Trace scheduling Abstract interpretation Assembly language Compiler optimizations Programming language implementation Software engineering
27	Optimizing and Reverse Engineering Itanium Binaries Noah Snavely EPIC (Explicitly Parallel Instruction Computing) architectures, such as the Intel IA-64 (Itanium), address common Add to Reading List Source URL: www.cs.arizona.edu Language: English - Date: 2010-09-27 23:22:30 Compiler optimizations Branch predication Itanium Explicitly parallel instruction computing Predicate Instruction scheduling Static single assignment form Instruction set Subroutine Computer architecture Computing Instruction set architectures
28	Inter-Block Scoreboard Scheduling in a JIT Compiler for VLIW Processors Technical Report A/392/CRI Benoˆıt Dupont de Dinechin STMicroelectronics STS/CEC Add to Reading List Source URL: www.cri.ensmp.fr Language: English - Date: 2008-06-04 03:10:36 Computing Operations research Instruction scheduling Very long instruction word Scheduling No instruction set computing Block scheduling Schedule List scheduling Education Scheduling algorithms Planning
29	Time-Indexed Formulations and a Large Neighborhood Search for the Resource-Constrained Modulo Scheduling Problem Benoˆıt Dupont de Dinechin STMicroelectronics STS/CEC 12, rue Jules Horowitz - BP 217. FGrenoble b Add to Reading List Source URL: www.cri.ensmp.fr Language: English - Date: 2007-06-06 10:50:57 Operations research Computing Job shop scheduling Mathematical optimization Multiplicative order Scheduling Modulo Very long instruction word Software pipelining Compiler optimizations Modular arithmetic Mathematics
30	The Regular Unwinding Framework Benoˆıt Dupont de Dinechin STMicroelectronics AST Embedded Systems Research Laboratory Via Cantonale 16E 6928 Manno Switzerland Abstract Add to Reading List Source URL: www.cri.ensmp.fr Language: English - Date: 2006-05-17 11:18:31 Applied mathematics Scheduling Mathematics Instruction scheduling Job shop scheduling Interval graph Operations research Planning Scheduling algorithms

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